This disclosure relates to semiconductor memory devices, and more particularly, to flash memory devices.
In general, a flash memory device includes a page buffer for programming or reading a large quantity of data within a short time. Therefore, the program operation or read operation of the flash memory device is performed by the page buffer on a page basis.
FIG. 1 is a schematic block diagram of a flash memory device in the related art. It should be noted that only a memory cell block 11 and page buffers 12 of a flash memory device 10 are shown in FIG. 1.
The memory cell block 11 is connected to each of the page buffers 12 through a plurality of bit lines BLe1, BLo1 to BLeK, BloK (where K is an integer). In the program operation of the flash memory device 10, data to be programmed (not shown) are stored in the page buffers 12. The page buffers 12 output data to memory cells (not shown) of the memory cell block 11 through the corresponding bit lines BLe1 to BLeK or BLo1 to BloK in response to a program control signal (PGM) output from a control unit (not shown). For example, a case where the memory cells connected to the bit lines BLe1 to BleK are programmed will be described in more detail with reference to FIG. 2.
As shown in FIG. 2, in the program operation, when a bit line control signal (VIRPWR) is enabled, a discharge signal (DISCHe) is enabled. As a result, the bit lines BLe1 to BleK are precharged with a voltage (VCC) level according to the bit line control signal (VIRPWR). Thereafter, the discharge signal (DISCHe) is disabled and bit line select signals (BSLe1 to BSLeK) and the program control signal (PGM) are enabled. As a result, the bit lines BLe1 to BleK are connected to sensing nodes (not shown) of the page buffers 12, respectively.
In the case where data “0” is stored in each of the page buffers 12, i.e., memory cells of a corresponding page are all programmed, current flows to the ground through a current path having the bit lines BLe1 to BLeK, the sensing nodes and a latch circuit (not shown) of the page buffer, so that the bit lines BLe1 to BleK are discharged to a ground voltage level. In the case where the page buffers 12 output data “0” to the bit lines BLe1 to BLeK at the same time according to the program control signal (PGM) as described above (i.e., the bit lines BLe1 to BLeK are discharged at the same time), the ground voltage of the flash memory device 10 may rise to a positive voltage. This will be described below in more detail.
For example, in the case where memory cells included in one page of the memory cell block 11 is 2 Kbytes, a peak current, which flows to the ground through page buffers having a number corresponding to that of memory cells in the program operation, is increased. If the increased current flows to the ground through the page buffers 12, the ground voltage level of the flash memory device 10 rises due to a voltage drop generated by the load of the page buffers 12 themselves. That is, a ground voltage bouncing phenomenon is generated. If the ground voltage rises as described above, a problem arises because a flash memory device malfunctions. More particularly, problems incurred by the ground voltage bouncing phenomenon is more profound in a cache program operation using a page buffer having a dual latch structure.
To be more specific, in the cache program operation, a data output operation in which a program is performed and a data input operation in which new data are received are performed at the same time in the page buffer having the dual latch structure. That is, while data stored in a main latch (not shown) are programmed into memory cells, new data for a next program operation are input to a cache latch (not shown).
In general, when data are input to the cache latch, data I/O nodes YG1 to YGK become a ground voltage level. As a result, data “0” is input to the cache latch. As data stored in the main latch is programmed into the memory cells, however, a ground voltage level rises. Therefore, unwanted erroneous data may be input to the cache latch. That is, even though data “0” must be input to the cache latch, data “1,” can be input to the cache latch as the ground voltage level rises. As a result, since erroneous data is programmed into the memory cells, the error occurrence ratio rises in the program operation of the flash memory device.